In recent years, improvements in performance, as well as increased integration of semiconductor devices, have resulted in a further reduction in line width of wire patterns and multilayer structures with more layers. Layer planarization in each process plays an important role in improvement of accuracy in photolithography. Chemical mechanical polishing (CMP) is the most well-known planarization technique in the art and may be classified as oxide layer CMP, metal CMP, and polysilicon CMP, depending on the target material.
Examples of a semiconductor process that employ CMP to polish an oxide layer include an interlayer dielectric (ILD) process and a shallow trench isolation (STI) process. The ILD process is a process for removing excess from a silicon oxide layer formed for interlayer insulation, and the STI process is a process for isolating devices from each other through formation of trenches for insulation between chips.
Although silica (SiO2) slurries have generally been used when initially polishing the oxide layer, cerium oxide (CeO2) slurries are commonly used when polishing the oxide layer to achieve high planarization for reduction in design rule and thickness of devices. Cerium oxide slurries exhibit high polishing selectivity, making them ideal for wafers comprising heterogeneous films. That is, since the cerium oxide slurries have a very high polishing rate with respect to a silicon oxide layer and a very low polishing rate with respect to a silicon nitride (Si3N4) layer, the cerium oxide slurries enable polishing of a silicon nitride portion of a heterogeneous layer without having any impact upon a polished silicon oxide portion, when used for polishing the silicon oxide layer and the silicon nitride layer with step portions formed thereon. The cerium oxide slurries make it possible to achieve broad planarization and accurate control of polishing thickness when applied to oxide layer CMP.
The cerium oxide slurries have a higher polishing rate than the silica slurries with respect to a flat silicon oxide layer (that is, a flat wafer) having no groove or protrusion. However, when the cerium oxide slurries are applied to polishing of a patterned silicon oxide layer having grooves or protrusions, the initial polishing rate of the patterned oxide layer is very low and then increases as the step portions are gradually removed from the oxide layer. That is, the cerium oxide slurries have a problem of low initial polishing rate when polishing the patterned oxide layer.
Such a problem is referred to as initial loading effect. In practical implementation, polishing is generally performed upon patterned oxide films having grooves or protrusions thereon, thereby causing a problem relating to an initial loading effect. To solve such a problem in polishing the patterned oxide layer, silica slurries which do not cause the problem relating to an initial loading effect are initially used, followed by use of cerium oxide slurries. However, when both the silica slurries and the cerium oxide slurries are used in polishing the patterned oxide layer, there is a problem of deterioration in polishing efficiency due to replacement of the slurries during the polishing process.
In another approach for improving polishing efficiency, chemical additives for enhancing an initial loading effect are added to CMP slurries. In this case, however, there is a problem in that the additives increase abrasion of diamond particles in a diamond disc conditioner which increases the activity of the polishing pad, thereby reducing lifespan of the conditioner.
Additionally, to improve the initial loading effect, Sang-Ick Lee et al. suggest a technique for adjusting the particle size of the cerium oxide slurry particle to 100 nm or less (CMP-MIC, p. 163 (2000)). However, this technique is not suitable for practical application due to a very low absolute polishing rate despite the increase in the ratio of pattern polishing rate to blanket polishing rate.